The inventions disclosed and/or claimed herein relate in general to methods for fabricating a ferroelectric memory device. Particularly, the inventions relate to methods for fabricating a ferroelectric memory device in which a ferroelectric capacitor module is made highly dense.
Generally, in a semiconductor memory device, efforts have been made to develop a large capacity memory device in which a ferroelectric thin film is used in a ferroelectric capacitor so that the refresh limitation of the DRAM (dynamic random access memory) can be overcome.
Such a ferroelectric random access memory (xe2x80x9cFeRAMxe2x80x9d) which utilizes the ferroelectric thin film is a kind of nonvolatile memory device.
This FeRAM retains the stored information even when power is not applied, and its operating speed is comparable to the DRAM. Accordingly, this FeRAM is gaining attention as a next generation memory device.
The charge storing material for this Fe RAM device, is a ferroelectric thin film such as SrBi2Ta2O9 (xe2x80x9cSBTxe2x80x9d) and Pb(Zr,Ti)O3 (xe2x80x9cPZTxe2x80x9d).
The ferroelectric thin film has a dielectric constant of several hundreds to several thousands at the normal temperature, and has two stable remnant polarizations (Pr). Thus it is formed into a form of a thin film to use it in the nonvolatile memory.
The nonvolatile memory device which uses the ferroelectric thin film utilizes a hysteresis characteristic to store xe2x80x981sxe2x80x99 and xe2x80x980sxe2x80x99 in accordance with the remnant polarization which is present when the electric field is removed after inputting the signals by adjusting the polarization direction in the direction of the imposed electric field.
In the FeRAM device, in the case where a ferroelectric thin film such as SrxBiy(TaiNbj)2O9 (xe2x80x9cSBTNxe2x80x9d) having a pervskite structure or the like is used for the ferroelectric capacitor, there are formed upper and lower electrodes which are generally made of Pt, Ir, Ru, IrO, RuO, Pt-alloy or the like.
FIGS. 1A (PRIOR ART) and 1B (PRIOR ART) illustrate a conventional fabricating method for a ferroelectric memory device.
As shown in FIG. 1A (PRIOR ART), a transistor fabricating process is carried out. A word line 12 is formed on a semiconductor substrate 11, and a source/drain 13 is formed at the both sides of the word line 12.
Then an interlayer insulating film 14 is formed on the semiconductor substrate 11, and then, the interlayer insulating film 14 is selectively patterned to form a plugging contact hole so as to expose the source/drain 13.
Then polysilicon is deposited on the entire surface of the structure, and then, an etchback or a chemical-mechanical polishing (CMP) is carried out, thereby forming a polysilicon plug 15.
Then a barrier film 16 is formed on the polysilicon plug 15, and then, an etchback or a chemical-mechanical polishing is carried out, thereby completely filling the plugging contact hole.
Under this condition, although it is not illustrated in the drawings, the barrier film 16 consists of a stacking of a Ti layer and a TiN layer, and TiSi2 is formed by heat-treating the boundary between the Ti layer and the polysilicon plug 15.
Then an adhesive layer 17 is formed on the interlayer insulating film 14 which includes the barrier film 16. Then the adhesive layer 17 is selectively patterned to completely expose the barrier film 16, and to expose a part of the interlayer insulating film 14. Thus the adhesive layer 17 is formed for reinforcing the adhesive force between the interlayer insulating film 14 and a storage electrode to be formed later.
Then the storage electrode 18, a ferroelectric thin film 19 and a plate electrode 20 are sequentially formed on the interlayer insulating film 14 and on the adhesive layer 17.
Then as shown in FIG. 1B (PRIOR ART), first the plate electrode 20 is patterned, and then, the ferroelectric thin film 19 and the storage electrode 18 are sequentially patterned, thereby forming a vertically stacked capacitor.
Here, reference codes 18axcx9c20a indicate the respective patterned portions. That is, reference code 18a indicates the storage electrode, 19a indicates the ferroelectric thin film, and 20a indicates the plate electrode.
However, in the above described conventional technique, the deposition process and the etching process have to be carried out for two or three times respectively after depositing the adhesive layer 17.
Accordingly, the fabricating process is complicated. Further, Pt, Ir, IrO2, Ru, RuO2 or the like is used for the storage electrode and for the plate electrode, while SBT, PZT, BLT or the like is used for the ferroelectric thin film. Thus the etching process is very difficult. Further, in the case where a 3-dimensional capacitor is fabricated, the mass production of the capacitor becomes difficult.
Further, according as the density of the device is increased, the size of the capacitor is gradually decreased, and the etching loss is gradually increased. Therefore, a fabricating process which can alleviate the burden of the etching process is demanded.
Further, in order to obtain the ferroelectric properties of the: FeRAM, there are carried out a crystallizing heat treatment and a degradation-compensating heat treatment after the deposition of the ferroelectric material. Accordingly, the characteristics of the oxidation preventing film have to be reinforced, so that the polysilicon plug under the storage electrode can be protected.
When the ferroelectric material and the storage electrode are etched after etching the plate electrode, an alignment margin for the masking process has to be secured. For this purpose, the storage electrode is given a far larger width than the plate electrode, and this becomes an impediment in the way toward a high density.
The fabricating methods prescribed by the inventions described herein overcome the above described disadvantages of the conventional techniques. Our fabrication methods form a high density ferroelectric memory device wherein the burden of etching the storage electrode, the plate electrode and the ferroelectric thin film is alleviated, and the fabricating process is simplified with respect to conventional techniques.
Various of our claimed methods feature: sequentially forming a seed layer and a sacrificial layer on a semiconductor substrate; selectively etching the sacrificial layer to form a loop shaped sacrificial layer pattern; simultaneously forming first and second electrodes on the seed layer; removing the sacrificial layer pattern; etching the seed layer (thus exposed) after removal of the sacrificial layer pattern; and forming a ferroelectric thin film by carrying out a spin-on process on an entire surface including the first and second electrodes.
In another respect, various of our claimed methods for fabricating a high density ferroelectric memory device feature: forming an insulating film on a semiconductor substrate; selectively etching the insulating film to form a contact hole so as to expose a part of the semiconductor substrate; forming a plug to bury it into the contact hole; forming a barrier film on the plug to completely fill the contact hole; sequentially forming a seed layer and a sacrificial layer on the insulating film including the barrier film; selectively etching the sacrificial layer to form a loop shaped sacrificial layer pattern; simultaneously forming first and second electrodes on the seed layer thus exposed after formation of the sacrificial layer pattern; removing the sacrificial layer pattern; etching the seed layer thus exposed after removal of the sacrificial layer pattern; and forming a ferroelectric thin film by carrying out a spin-on process on the entire surface including the first and second electrodes.